Embodiments of the present invention relate to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, such that a fabrication process of the semiconductor device having a buried gate is simplified and the number of problems caused by such a fabrication process is minimized.
With the increasing integration degree of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM), an area occupied by a Metal Oxide Semiconductor (MOS) transistor is gradually decreasing. As a result, a channel length of the MOS transistor is also decreasing, resulting in the occurrence of a short channel effect. Specifically, if a short channel effect occurs in an access MOS transistor used in a memory cell of the DRAM, a threshold voltage of the DRAM cell is decreased, and a leakage current of the DRAM cell is increased, such that refresh characteristics of the DRAM is consequently decreased.
Therefore, as an improved MOS transistor capable of restricting the short channel effect regardless of the increasing integration degree of the memory device, a recess gate MOS transistor having a longer channel length has recently been proposed.
However, a highly-integrated semiconductor device, such as a highly-integrated DRAM based on 60 nm technology, has difficulty in obtaining desired requirements using only the recess gate MOS transistor. Specifically, as the technology level moves close to a level of 40 nm or less, it is difficult to form a gate structure, a bit line structure, a contact structure, and the like. Although it is assumed that such structures can be formed, it is also difficult to obtain a resistance characteristic, a refresh characteristic, a guarantee of low fails, and a breakdown voltage characteristic that are capable of satisfying element characteristics of the semiconductor device.
Accordingly, in order to increase the integration degree, reduce the number of fabrication processes, and improve element characteristics such as a leakage characteristic, an improved semiconductor device having a buried gate has recently been developed and come into the market.
A semiconductor device having a buried gate is buried under the surface of the semiconductor substrate, so that it provides a relatively long effective channel length. A method for manufacturing the buried gate forms a trench and buries a gate in the trench, so that interference between a bit line and a gate can be minimized and the number of stacked films can be decreased. In addition, capacitance of the entire cell is decreased so that refresh characteristics can be increased.
However, in accordance with the conventional semiconductor device having such a buried gate, a gate of the core/peri region is formed on a semiconductor substrate whereas a gate of the cell region is buried in the semiconductor substrate, so that there is a difference in height (i.e., a step height) between the cell region and the core/peri region.
In accordance with the related art for solving the step height problem, a bit line of the cell region and the gate of the core/peri region are simultaneously formed.
However, according to the above-mentioned related art, a poly part for forming the bit line of the cell region and another poly part for forming the gate of the core/peri region are excessively deposited in the vicinity of a boundary between the cell region and the core/peri region, so that a variety of problems are unexpectedly encountered when the excessively deposited poly parts are removed.